The present invention is related generally to the field of Rapid Thermal Processing (RTP) of a workpiece and, more particularly, to a radiation shield including a plurality of segments for use in applying controlled heat to the workpiece.
In the production of devices including, but not limited to semiconductors, optoelectronic devices, flat panel displays and MEMS (Micro Electro-Mechanical Systems), at least some processing steps may require the application of controlled heat. For example, in the instance of semiconductors, certain processing steps require the application of heat to wafers and other such workpieces to accomplish annealing. In particular, ion implantation is often used to introduce a dopant in selected areas of a wafer. An RTP anneal is thereafter applied, since the ion implantation process damages the crystal lattice structure of the exposed, selected areas of the wafer, leaving the implanted dopant atoms in interstitial sites where they are electrically inactive. Annealing serves to move the dopant atoms into substitutional sites in the lattice to render them electrically active, and to repair the damage to the crystal lattice structure that occurs during ion implantation.
Unfortunately, annealing the device side of a semiconductor wafer can produce undesirable effects in the absence of precision control. At high temperatures, dopant atoms may diffuse into the wafer at much higher rates, with most of the diffusion occurring at the peak annealing temperature that is required to activate the dopants. With increasing performance demands for semiconductor wafers and decreasing device sizes, it is necessary to produce increasingly shallow and abruptly defined junctions. In order to accommodate these demands and ever smaller device sizes, it is desirable to control a wafer anneal heating profile as precisely as possible in a way which subjects the wafer to temperature conditions which serve to activate the dopants while, at the same time, limiting diffusion of the dopants.
One well-known configuration for use in implementing a rapid annealing process, in a single wafer approach, utilizes heating elements which generate radiation to which a wafer is directly subjected. One possible implementation of this approach is shown as FIG. 3a of U.S. Pat. No. 6,054,684, issued to Pas, et al. (hereinafter Pas) which is repeated as FIG. 1 of the present application, having alternative reference numbers applied thereto. A heat processing arrangement, generally illustrated by the reference numeral 10, includes a wafer holder 12 and heaters 14. The latter may be comprised of resistive heating elements or lamps. A shutter system 16 is positioned between heaters 14 and a wafer (not shown) supportable on wafer holder 12. Shutters 16 are provided for selectively blocking energy from heaters 14 from reaching the wafer.
As is recognized by Pas, the described configuration is problematic since the interposition of the shutter system, between the wafer and heating elements, produces shadowing on the wafer with the shutters in their open position. The result of such shadowing is non-uniform heating of the wafer surface.
While Pas attempts to reduce the shadowing problem by suggesting the use of reflective coatings on the shutters, the overall configuration is considered as unacceptable in view of the teachings of the present invention. Specifically, it is submitted that this shadowing results in shadowed device areas which would be under-annealed as a result of exposure to only indirect radiation from heaters 14. Increasing exposure time in order to properly heat treat the shadowed areas is likely to produce excessive dopant diffusion problems in areas of a wafer that are directly exposed to the heaters.
It is of interest that FIG. 3 of U.S. Pat. No. 6,259,062, issued to Pan, and repeated here as FIG. 2, having alternative reference numbers applied thereto, includes a remarkably similar arrangement to that of Pas. Pan describes a system, generally indicated by the reference number 30 in which a wafer 32 is supported on a pedestal 33 in a process chamber 34 so that the wafer may be exposed to a plurality of heating sources 36 such as radiant heat lamps that are arranged above and below the wafer. As is common practice in the prior art, a reflective surface 38 is positioned outward of the heat lamps. Rather than using shutters like Pas, however, two radiation absorbing material members 40 are translationally movable in directions indicated by double-headed arrows 42 such that material 40 may be slidably interposed between lamps 36 and wafer 32 (both above and below the wafer) or moved laterally out of the region which lies directly between lamps 36 and wafer 32 (see FIGS. 1 and 2 of Pan). It is important to understand, however, that the Pan patent is directed to using heat absorbing medium 40 in post-process cooling of wafer 32 for purposes of improving system throughput. That is, the patent appears to be narrowly tailored to cooling the wafer following completion of processing. To that end, medium 40 slides into position between the wafer and reflective surface 38, both above and below the wafer, after processing is complete so as to absorb radiant heat 44 from the wafer in order to more rapidly cool the wafer for removal. System throughput may be enhanced, for example, since a heat sensitive robot arm is sooner able to pick up the cooled wafer. In this regard, it is noted that FIG. 2 clearly represents a post-process condition since no heat is shown emanating from heating sources 36.
While the arrangement of Pan does not exhibit the shadowing problem of the shutter arrangement of Pas, it is submitted that another important problem would be introduced in any attempt to use this configuration in the context of Pas, or generally as part of a rapid thermal process, as will be discussed immediately hereinafter.
Still referring to FIG. 2, implementation of a heating profile that is controlled, at least in part, using medium 40 would be problematic for a particular reason. Specifically, it is recognized herein, as will be further described, that the act of translationally moving medium 40 to an interposed position would progressively block direct radiation between lamps 36 and wafer 40. If actual processing were underway, with the lamps emitting radiation, the wafer would be highly non-symmetrically exposed to radiation, resulting in unpredictable and unacceptable consequences insofar as RTP contemplated by the present invention. Again, however, it is noted that Pan appears to be narrowly tailored to its stated post-process purpose.
The present invention provides a highly advantageous apparatus and method which are submitted to resolve the foregoing difficulties and problems while providing still further advantages.